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| Ordering number : EN*5281A CMOS LSI LC99012A-S Black-and-White CCD Timing Generator Preliminary Overview The LC99012A-S is a timing generator for the 1/5-inch LC9947G and LC9948G and the 1/6-inch LC9949G black-and-white CCD image sensors. Package Dimensions unit: mm 3190-SQFP64 [LC99012A-S] Features * 5 V single-voltage power supply * Generates all pulses required for CCD drivers. * Generates all pulses required for video signal processing. * Built-in synchronizing signal generator that supports both EIA and CCIR. * Includes buffer circuits for directly driving the CCD horizontal transfer and reset gates. * Includes light metering and control systems for an automatic electronic iris function. * Fixed rate-of-change control allows a smooth electronic iris function to be implemented (an iris state output is provided). * Supports AGC control and a light metering mode that compensates for backlighting. * Selectable CCD storage mode (non-interlaced or interlaced) * Selectable TV scan mode (non-interlaced or interlaced) * Allows all types of external synchronization. * Built-in EXT-C.SYNC sync separator circuit * Built-in phase comparator for external synchronization * Control from external electronic shutter pulses and frame shift pulses supports one-shot imaging. * Package: 0.5 mm lead pitch flat package (SQFP-64) * Flickerless function * Sensitivity-increasing function SANYO: SQFP64 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 22896HA (OT) No. 5281-1/6 LC99012A-S Specifications Absolute Maximum Ratings at VSS = 0 V Parameter Maximum supply voltage Input and output voltages Allowable power dissipation Operating temperature Storage temperature Soldering heat resistance Input and output currents Note: * Per individual I/O reference cell I I, I O Symbol VDD max VI, VO Pd max Topr Tstg Hand soldering: 3 seconds Reflow soldering: 10 seconds Ta 65C Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 290 -30 to +65 -55 to +125 350 235 20* Unit V V mW C C C C mA Allowable Operating Ranges at Ta = -30 to +65C, VSS = 0 V Parameter Supply voltage Input voltage range Symbol VDD VIN Conditions min 4.5 0 typ 5.0 max 5.5 VDD Unit V V DC Characteristics: Input and Output Levels at VSS = 0 V, VDD = 4.5 to 5.5 V, Ta = -30 to +65C See the note on next page. Parameter Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Output high-level voltage Output low-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Input leakage current Output leakage current Pull-up resistance Pull-down resistance Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VIH4 VIL4 VIH5 VIL5 VOH1 VOL1 VOL2 VOH3 VOL3 VOH4 VOL4 VOH5 VOL5 VOH6 VOL6 VOH6 VOL7 IIL IOZ RUP RDN TTL levels: (6) TTL levels: (6) CMOS levels: (1), (3) CMOS levels: (1), (3) CMOS levels, Schmitt inputs: (4) CMOS levels, Schmitt inputs: (4) CMOS levels, inputs with pull-up resistors: (2) CMOS levels, inputs with pull-up resistors: (2) CMOS levels, inputs with pull-up resistors: (5) CMOS levels, inputs with pull-up resistors: (5) IOH = -3 mA: (6), (13), (14), (15) IOL = 3 mA: (6), (13), (14), (15) IOL = 3 mA: (9) IOH = -6 mA: (12) IOL = 6 mA: (12) IOH = -6 mA: (7) IOL = 2 mA: (7) IOH = -30 mA: (11) IOL = 10 mA: (11) IOH = -12 mA: (8) IOL = 12 mA: (8) IOH = -12 mA: (10) IOL = 6 mA: (8) VI = VSS, VDD: (1), (3), (4), (6) In high-impedance output mode: (6), (9), (13) (2) (5) -10 -10 10 25 20 50 VDD - 1.5 0.4 +10 +10 40 100 VDD - 2.1 0.4 VDD - 2.1 0.4 VDD - 2.1 0.4 VDD - 2.1 0.4 VSS - 2.1 0.4 0.4 0.7 VDD 0.3 VDD 0.7 VDD 0.3 VDD 0.8 VDD 0.2 VDD 0.7 VDD 0.3 VDD Conditions min 2.2 0.8 typ max Unit V V V V V V V V V V V V V V V V V V V V V V V A A k k No. 5281-2/6 LC99012A-S Note: The applicable pin sets are defined as follows: Input (1) ......AI, CKI (2) ......FLESS, STR, TEST (3) ......EXT1, EXT2, KISYU, TV (4) ......HR, SELMET1, SELMET2, VR (5) ......CCDSCAN, EXT3, EXT4, MSENS, SENS, SSGSCAN I/O (6) ......STEPSTOP Output (7) ......PCO (8) ......DHTR (9) ......IRRES (10) ....A0, CKO (11) ....DHT1, DHT2 (12) ....DS1, DS2 (13) ....AGCC2, IRSTA (14) ....CLK14M, CLP1, CLP2, FLD, HD, NSUB1, NSUB2, VD (15) ....CBLK, C.SYNC, NSUB3, PBLK, VI1 to VI4, VS1 to VS4 * ......VIDI, VIDO, DCH, DCL, IRIS (These pins are not covered in the DC characteristics.) Pin Assignment I/O I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: Unconnected pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol VSS PCO AI AO CKI CKO CCDSCAN SSGSCAN CLK14M HD VD FLD VDD KISYU HR VR VSS SELMET1 SELMET2 EXT1 EXT2 EXT3 EXT4 VDD STEPSTOP SENS MSENS FLESS STR NSUB3 NSUB2 NSUB1 I/O P O I O I O I I O O O O P I I I P I I I I I I P B I I I I O O O No. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Symbol DCL DCH IRIS IRRES VIDO VIDI IRSTA AGCC2 VDD TV C.SYNC CBLK PBLK CLP2 CLP1 VSS DS1 DS2 VDD DHT2 DHT1 DHTR VSS VS3 VS2 VS1 VS4 VI4 VI2 VI3 VI1 TEST I/O I I I O O I O O P I O O O O O P O O P O O O P O O O O O O O O I Note: All VDD and VSS pins must be connected to the power supply or ground. Do not leave any of these pins open. No. 5281-3/6 LC99012A-S Block Diagram No. 5281-4/6 LC99012A-S Pin Functions Pin No. 1 2 3 4 Symbol GND PCO AI AO O I O Phase comparator output PCO output signal low-pass filter amplifier input PCO output signal low-pass filter amplifier output Reference clock input (resonator inverter input) LC9947G: 28.63636 MHz LC9948G: 28.375 MHz LC9949G: 14.31818 MHz Resonator inverter output Low/open: CCD interlaced storage mode High: CCD non-interlaced storage mode Low/open: C.SYNC interlaced mode High: C.SYNC non-interlaced mode LC9947G/9949G: 14.31818 MHz LC9948G: 14.1875 MHz HD output VD output Field identifier signal High: odd Low: even Must be tied high if SSGSCAN is high. I/O Function 5 CKI I 6 7 8 9 10 11 CKO CCDSCAN SSGSCAN CLK14M HD VD O I I O O O 12 FLD O 13 14 15 16 17 18 19 20 21 22 23 24 25 VDD KISYU HR VR GND SELMET1 SELMET2 EXT1 EXT2 EXT3 EXT4 VDD STEPSTOP I I I I I I I I/O Normally used to control the electronic iris step (rate of change) Low: 1/8 Hifh: 1/16 Sensitivity increasing switch Low/open: normal High: Increased sensitivity mode Increased sensitivity mode type switching Low or open: In field units High: In single scan line (1H) units Flickerless mode* switch Low: Flickerless mode High/open: normal CCD storage mode control This pin must be left open or tied high when the LC99012A-S is used with an LC9947G/49G, and must be tied low when used with an LC9948G. CCD NSUB pulses CCD NSUB pulses CCD NSUB pulses Low: test mode High/open: normal operating mode CCD imaging block transfer clock (o1) CCD imaging block transfer clock (o3) CCD imaging block transfer clock (o2) CCD imaging block transfer clock (o4) CCD imaging block transfer clock (oS4) Light metering mode control Light metering mode control External synchronization mode control External synchronization mode control CCD drive external control mode control CCD drive external control mode control I I I Must be tied high when used with the LC9949G. Otherwise must be tied low. Horizontal reset, C.SYNC reset, and vertical reset pulse input Vertical reset pulse input and external synchronization mode setup 26 SENS I 27 MSENS I 28 FLESS I 29 30 31 32 33 34 35 36 37 38 STR NSUB3 NSUB2 NSUB1 TEST VI1 VI3 VI2 VI4 VS4 I O O O I O O O O O Note: * Flickerless mode can be used when the auto-iris function is off, i.e. when EXT3 is high and EXT4 is low. Continued on next page. No. 5281-5/6 LC99012A-S Pin No. 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 Symbol VS1 VS2 VS3 GND DHTR DHT1 DHT2 VDD DS2 DS1 GND CLP1 CLP2 PBLK CBLK C.SYNC TV VDD AGCC2 I/O O O O CCD imaging block transfer clock (oS1) CCD imaging block transfer clock (oS2) CCD imaging block transfer clock (oS3) Function CCD output block reset pulse O O CCD horizontal transfer clock (oH1) CCD horizontal transfer clock (oH2) O O CCD output floating level sampling pulse CCD output video signal sampling pulse O O O O O I OPB clamp pulse OPB clamp pulse Pre-blanking pulse Composite blanking pulse Composite sync pulse Low: EIA (LC9947G/49G) High: CCIR (LC9948G) O AGC detection signal weighting processing pulse Electronic iris state output High: The iris is in the fully stopped down state. Low: The iris is in the fully open state. High-impedance: The iris is in an appropriate state. Analog switch input for iris detection signal window processing Analog switch output for iris detection signal window processing Reset (discharge) pulse that is input by the iris signal detection (integration) circuit Iris integration signal input High-level reference voltage for the iris level detection comparator Low-level reference voltage for the iris level detection comparator 58 IRSTA O 59 60 61 62 63 64 VIDI VIDO IRRES IRIS DCH DCL I O O I I I s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice. No. 5281-6/6 |
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